Partial line cache write injector for direct memory access write
US8806153B2 · kind B2 · utility
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10References
23Claims
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Key dates
| Filing date | Feb 22, 2011 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Oct 20, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache within a computer system receives a partial write request and identifies a cache hit of a cache line. The cache line corresponds to the partial write request and includes existing data. In turn, the cache receives partial write data and merges the partial write data with the existing data into the cache line. In one embodiment, the existing data is “modified” or “dirty.” In another embodiment, the existing data is “shared.” In this embodiment, the cache changes the state of the cache line to indicate the storing of the partial write data into the cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.