Small footprint phase change memory cell
US8809828B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 13, 2014 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Feb 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/063
Abstract
An example embodiment disclosed is a phase change memory cell in a semiconductor wafer. The semiconductor wafer includes a first metalization layer (Metal 1). The phase change memory cell includes an insulating substrate defining a non-sublithographic via. The non-sublithographic via is located on the first metalization layer and includes a bottom and a sidewall. Intermediate insulating material is positioned below the insulating substrate. The intermediate insulating material defines a sublithographic aperture passing through the bottom of the non-sublithographic via. A bottom electrode is positioned within the sublithographic aperture, and is composed of conductive non-phase change material. The non-sublithographic via includes phase change material positioned within. The phase change material is electrically coupled to the bottom electrode. A liner is positioned along the sidewall of the non-sublithographic via. The liner is electrically coupled to the phase change material and is composed of the conductive non-phase change material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.