Integrated circuits and methods for fabricating integrated circuits with cladded non-planar transistor structures
US8809947B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2013 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | May 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/024
Abstract
In an exemplary embodiment, a method for fabricating integrated circuits includes providing a semiconductor substrate. The method etches the semiconductor substrate to form a non-planar transistor structure having sidewalls. On a standard (100) <110> substrate the fin sidewalls have (110) surface plane if the fins are aligned or perpendicular with the <110> wafer notch. The method includes depositing a sacrificial liner along the sidewalls of the non-planar transistor structure. Further, a confining material is deposited overlying the semiconductor substrate and adjacent the sacrificial liner. The method includes removing at least a portion of the sacrificial liner and forming a void between the sidewalls of the non-planar transistor structure and the confining material. A cladding layer is epitaxially grown in the void. Since the sidewall growth is limited by the confining material, a cladding layer of uniform thickness is enabled on fins with (110) sidewall and (100) top surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.