Inventor · Watervliet, NY, US

Ajey Poovannummoottil Jacob

226Patents

15h-index

106Co-inventors

85Inventor score

Filing activity: Jun 18, 2009 → Dec 1, 2022

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8716156B1	Methods of forming fins for a FinFET semiconductor device using a mandrel oxidation process	Electricity	44	Active
US10429582B1	Waveguide-to-waveguide couplers with multiple tapers	Physics	37	Active
US10816726B1	Edge couplers for photonics applications	Physics	28	Active
US9343300B1	Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel region	Electricity	24	Active
US9147748B1	Methods of forming replacement spacer structures on semiconductor devices	Electricity	24	Active
US9269628B1	Methods of removing portions of at least one fin structure so as to form isolation regions when forming FinFET semiconductor devices	Electricity	23	Active
US8673718B2	Methods of forming FinFET devices with alternative channel materials	Electricity	22	Active
US9349658B1	Methods of forming fin isolation regions on finFET semiconductor devices using an oxidation-blocking layer of material	Electricity	20	Active
US9165837B1	Method to form defect free replacement fins by H2 anneal	Electricity	20	Active
US8580642B1	Methods of forming FinFET devices with alternative channel materials	Electricity	19	Active
US9147730B2	Methods of forming fins for FinFET semiconductor devices and selectively removing some of the fins by performing a cyclical fin cutting process	Electricity	19	Active
US9093496B2	Process for faciltiating fin isolation schemes	Electricity	17	Active
US11029465B1	Micro-ring modulator	Physics	17	Active
US9972537B2	Methods of forming graphene contacts on source/drain regions of FinFET devices	Electricity	16	Active
US8450818B2	Methods of forming spin torque devices and structures formed thereby	Electricity	16	Active
US9831131B1	Method for forming nanowires including multiple integrated devices with alternate channel materials	Electricity	15	Active
US9023705B1	Methods of forming stressed multilayer FinFET devices with alternative channel materials	Electricity	14	Active
US9263587B1	Fin device with blocking layer in channel region	Electricity	14	Active
US10217846B1	Vertical field effect transistor formation with critical dimension control	Electricity	14	Active
US9318342B2	Methods of removing fins for finfet semiconductor devices	Electricity	13	Active
US9318552B2	Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices	Electricity	13	Active
US9362405B1	Channel cladding last process flow for forming a channel region on a FinFET device	Electricity	13	Active
US10641956B1	Polarizers and polarization splitters phase-matched with a back-end-of-line layer	Physics	12	Active
US8809947B1	Integrated circuits and methods for fabricating integrated circuits with cladded non-planar transistor structures	Electricity	12	Active
US9117875B2	Methods of forming isolated germanium-containing fins for a FinFET semiconductor device	Electricity	11	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.