Stacked integrated circuit package system with face to face stack configuration
US8810018B2 · kind B2 · utility
5Cited by
10References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2006 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Sep 1, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked integrated circuit package system is provided forming a first molded chip comprises attaching a conductor on a wafer, applying an encapsulant around the conductor, and exposing a surface of the conductor in the encapsulant, attaching a first electrical interconnect on the conductor of the first molded chip and stacking an integrated circuit device on the first molded chip with an electrical connector of the integrated circuit device connected to the conductor of the first molded chip with the first electrical interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.