Systems and methods of updating read voltages in a memory
US8811081B2 · kind B2 · utility
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1References
18Claims
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Key dates
| Filing date | Dec 9, 2011 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Apr 18, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes receiving hard bit data and soft bit data corresponding to a portion of a memory, where each storage element of the memory stores multiple bits per storage element. The hard bit data and the soft bit data is received in connection with reading a single bit of the multiple bits from each storage element in the portion of the memory based on one or more first read voltages. One or more second read voltages based on the hard bit data and the soft bit data are generated in response to a read voltage update operation. The memory reads data from the portion of the memory using the one or more second read voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.