Methods for fabricating integrated circuits having confined epitaxial growth regions
US8815685B2 · kind B2 · utility
4Cited by
0References
18Claims
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Assignee
Inventors
Key dates
| Filing date | Jan 31, 2013 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Jan 31, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02658
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods are provided for fabricating integrated circuits. In accordance with one embodiment, the method includes forming a portion of a semiconductor substrate at least partially bounded by a confinement isolation material. A liner dielectric is formed overlying the confinement isolation material and is treated to passivate a surface thereof. An epitaxial layer of semiconductor material is then grown overlying the portion of semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.