Contact structure and method for variable impedance memory element
US8816314B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 12, 2012 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | May 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/10
Abstract
A memory element can include an opening formed within at least one insulating layer formed on an etch stop layer that exposes a first electrode portion and the etch stop layer at a bottom of the opening; a second electrode portion, formed on at least a side surface of the opening and in contact with the first electrode portion, the second electrode portion not filling the opening and being substantially not formed over a top surface of the at least one insulating layer; and at least one memory layer formed on a top surface of the at least one insulating layer and in contact with the second electrode portion, the at least one memory layer being reversibly programmable between at least two impedance states. Methods of forming such memory elements are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.