Multi-chip package cross-reference to related applications
US8816360B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 23, 2012 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Oct 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip package includes a lower substrate; at least two semiconductor chips stacked over the lower substrate and each defined with a via hole; an upper substrate coupled to a semiconductor chip positioned uppermost among the semiconductor chips; a light emitting part coupled to the lower substrate corresponding to the via hole; an electrowetting liquid lens coupled to a lower surface of the upper substrate for receiving a signal transferred from the light emitting part through the via hole; a light receiving part coupled to a sidewall of the via hole of each semiconductor chip configured to receive a signal from the electrowetting liquid lens.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.