Methods and materials useful for chip stacking, chip and wafer bonding
US8816485B2 · kind B2 · utility
1Cited by
10References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 18, 2012 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Sep 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.