PCB circuit modification from multiple to individual chip enable signals
US8817511B2 · kind B2 · utility
11Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2010 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | May 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor package is disclosed having a single CE signal during electrical test and a plurality of CE signals during normal operation thereafter. After electrical testing of the memory die during fabrication, the electrical traces carrying the single CE signal from the memory test pad matrix to each of the memory die may be severed. Severing the electrical traces from the memory test pad matrix electrically isolates the multiple electrical traces between the controller die and memory die, and allows separate and individual CE signals between the controller die and memory die during normal usage of the memory die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.