Data-masked analog and digital read for resistive memories
US8817530B2 · kind B2 · utility
10Cited by
5References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2012 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Nov 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An analog read circuit measures the resistance of each of a plurality of bits in an array of resistive memory elements. Data stored within a latch determines whether to selectively enable the analog read circuit. In an alternate embodiment, a sense amplifier is coupled to the latch and the array, and the data stored in the latch determines whether to selectively enable the sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.