High voltage gate formation
US8822289B2 · kind B2 · utility
7Cited by
18References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2012 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Feb 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
Embodiments described herein generally relate to methods of manufacturing charge-trapping memory by patterning the high voltage gates before other gates are formed. One advantage of such an approach is that a thin poly layer may be used to form memory and low voltage gates while protecting high voltage gates from implant penetration. One approach to accomplishing this is to dispose the layer of poly, and then dispose a mask and a thick resist to pattern the high voltage gates. In this manner, the high voltage gates are formed before either the low voltage gates or the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.