Patent · US Active

Method of fabricating MOS device

US8822297B2 · kind B2 · utility

0Cited by
2References
14Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 23, 2013
Grant dateSep 2, 2014
Priority date—
Expiry dateJan 23, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/021
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Provided is a method of fabricating a MOS device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer. A first implant process is performed to form source and drain extension regions in the substrate, wherein the gate conductive layer is covered by the hard mask layer. A process is of removing the hard mask layer is performed to expose the surface of the gate conductive layer. A second implant process is performed to form pocket doped regions in the substrate, wherein the gate conductive layer is not covered by the hard mask layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.