Semiconductor memory device having three-dimensionally arranged resistive memory cells
US8822971B2 · kind B2 · utility
11Cited by
3References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2012 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Sep 15, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/884
Abstract
Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.