Controlling clock input buffers
US8824235B2 · kind B2 · utility
6Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2009 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Dec 30, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit may have a clock input pin coupled to a buffer (24). The buffer may supply a clock signal (28) to an integrated circuit chip such as the memory. To conserve power, the buffer is powered down. When ready for use, the buffer is quickly powered back up. In one embodiment, in response to a predetermined number of toggles of the clock signal, the buffer is automatically powered up.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.