Wafer level image sensor packaging structure and manufacturing method of the same
US8828777B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2011 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | May 17, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a wafer level image sensor packaging structure and a manufacturing method of the same. The manufacturing method includes the following steps: providing a silicon wafer, dicing the silicon wafer, providing a plurality of transparent lids, fabricating a plurality of semi-finished products, performing a packaging process, mounting solder balls, and cutting an encapsulant between the semi-finished products. The manufacturing method of the invention has the advantage of being straightforward, uncomplicated, and cost-saving. Thus, the wafer level image sensor package structure is lightweight, thin, and compact. To prevent the image sensor chip from cracking on impact during handling, the encapsulant will be arranged on the lateral sides of the semi-finished products during the packaging process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.