Spacer profile engineering using films with continuously increased etch rate from inner to outer surface
US8828858B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2012 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Aug 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.