Host stop-transmission handling
US8832353B2 · kind B2 · utility
5Cited by
35References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2009 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Oct 13, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a controller and a memory array that stores partial-page data and complete-page data in separate areas. Data received from a host is sent from a memory controller to an on-chip cache prior to determining whether the data is partial-page data or complete-page data. After a determination is made, the data is stored at an address in the corresponding area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.