Patent · US Active

Hardware verification using acceleration platform

US8832502B2 · kind B2 · utility

8Cited by

5References

16Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Manoj Dusanapudi · Bengaluru, IN
Wisam Kadry · Haifa, IL
Shakti Kapoor · Austin, US
Dimtry Krestyashyn · Haifa, IL
Shimon Landa · Kiryat Yam, IL
Amir Nahir · Tirat Karmel, IL
John A. Schumann · Austin, US
Gil Eliezer Shurek · Haifa, IL
Vitali Sokhin · Haifa, IL

Key dates

Filing date	Jul 25, 2012
Grant date	Sep 9, 2014
Priority date	—
Expiry date	Jan 11, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/263
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method includes executing a first post-silicon testing program by a reference model. During the execution of the first post-silicon testing program, one or more test-cases are generated. The first post-silicon testing program is executed in an offline generation mode. During execution of the first post-silicon testing program each test case is generated in a different memory location. After the execution, generating a second post-silicon testing program that is configured to execute the one or more test-cases. The method further includes executing the second post-silicon testing program on an acceleration platform.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.