Circuit to reduce peak power during transition fault testing of integrated circuit
US8832510B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2011 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Nov 9, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318594
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit for reducing peak power during transition fault testing of an integrated circuit (IC) includes a programmable register that receives scan shift and SDI (scan data in) signals. Input and output ports of the programmable register are connected together. A multiplexer is provided that has a first input port that is maintained asserted, and a second input port connected to the output port of the programmable register. A scan shift signal, which remains asserted during a scan shift operation and de-asserted during a scan capture operation, is provided at a select input port of the multiplexer. The output of the multiplexer is provided as an input to a clock gating cell. The clock gating cell selectively provides the clock signal to the scan-chain flip-flops in the IC based on the scan shift signal and a functional enable signal, and reduces peak power during transition fault testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.