Method for detecting and debugging design errors in low power IC design
US8832615B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 9, 2013 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | May 9, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for detecting anomalies in signal behaviors in a simulation of a low power IC includes receiving a circuit design and a power specification of the IC, determining at least one power sequence checking rule from the power specification, simulating the circuit design and the power specification to obtain a dump file, identifying at least one anomaly of the at least one power sequence checking rule based on the dump file, and generating information relevant to the identified anomaly of the at least one power sequence checking rule. The method further includes setting up a context in a debugger for debugging the anomaly by displaying a waveform of misbehaved signals associated with the anomaly in a waveform window, and a portion of the circuit design and/or a portion of the power specification associated with the anomaly in a text window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.