Structure and method to form input/output devices
US8836037B2 · kind B2 · utility
7Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 13, 2012 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Aug 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.