Plesiochronous clock generation for parallel wireline transceivers
US8836391B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2012 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Oct 2, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0067
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-N phase lock loop; and utilizing, by the at least one fractional-N phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-N phase lock loop are contained on a single integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.