Systems and methods for post-bonding wafer edge seal
US8841201B2 · kind B2 · utility
6Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2013 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Mar 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device is disclosed. A first substrate is arranged over a second substrate. A wafer bonding process is performed on the semiconductor device. First regions of the device are enclosed by the bonding process. Second regions of the device remain exposed. One or more processes are performed on the exposed second regions, after performing the wafer bonding process. The one or more processes include a fill process that forms a fill material within the exposed second regions. An edge seal material is applied on the first and second substrates after performing the one or more processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.