Self-adjusting latch-up resistance for CMOS devices
US8841732B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 3, 2011 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Dec 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/854
Abstract
CMOS devices (60, 61, 61′) having improved latch-up robustness are provided by including with one or both WELL regions (22, 29) underlying the source-drains (24, 25; 31, 32) and the body contacts (27, 34), one or more further regions (62, 62′, 62-2) doped with deep acceptors or deep donors (or both) of the same conductivity type as the corresponding WELL region and whose ionization substantially increases as operating temperature increases. The increase in conductivity exhibited by these further regions as a result of the increasing ionization of the deep acceptors or donors off-sets, in whole or part, the temperature driven increase in gain of the parasitic NPN and/or PNP bipolar transistors inherent in prior art CMOS structures. By clamping or lowering the gain of the parasitic bipolar transistors, the CMOS devices (60, 61, 61′) are less likely to go into latch-up with increasing operating temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.