Inventor · Fishkill, NY, US

Gan Wang

21Patents
7h-index
34Co-inventors
65Inventor score

Filing activity: May 19, 2000 → Jun 5, 2018

Most-cited inventions

PatentTitleAreaCited byStatus
US6396995B1 Method and apparatus for retaining and presenting at least one microsphere array to solutions and/or to optical imaging systems Chemistry; Metallurgy 109 Expired
US7901897B2 Methods of making arrays Chemistry; Metallurgy 54 Active
US8628952B2 Array kits and processing systems Chemistry; Metallurgy 44 Active
US8481415B2 Self-aligned contact combined with a replacement metal gate/high-K gate dielectric Electricity 17 Active
US8084346B1 Replacement metal gate method Electricity 16 Active
US8236632B2 FET structures with trench implantation to improve back channel leakage and body resistance Electricity 9 Active
US9171954B2 FinFET structure and method to adjust threshold voltage in a FinFET structure Electricity 7 Active
US8809953B2 FET structures with trench implantation to improve back channel leakage and body resistance Electricity 5 Active
US8772149B2 FinFET structure and method to adjust threshold voltage in a FinFET structure Electricity 4 Active
US8932949B2 FinFET structure and method to adjust threshold voltage in a FinFET structure Electricity 3 Active
US8592266B2 Replacement gate MOSFET with a high performance gate electrode Electricity 1 Active
US9034715B2 Method and structure for dielectric isolation in a fin field effect transistor Electricity 1 Active
US9105725B2 Semiconductor-on-insulator device including stand-alone well implant to provide junction butting Electricity 0 Active
US9337289B2 Replacement gate MOSFET with a high performance gate electrode Electricity 0 Active
US9312358B2 Partially-blocked well implant to improve diode ideality with SiGe anode Electricity 0 Active
US9252234B2 Partially-blocked well implant to improve diode ideality with SiGe anode Electricity 0 Active
US9059291B2 Semiconductor-on-insulator device including stand-alone well implant to provide junction butting Electricity 0 Active
US8841732B2 Self-adjusting latch-up resistance for CMOS devices Electricity 0 Active
US8969933B2 Replacement gate MOSFET with a high performance gate electrode Electricity 0 Active
US9209200B2 Methods for forming a self-aligned maskless junction butting for integrated circuits Electricity 0 Active
US10848960B2 Method and system for interaction between AP and modem, and storage medium Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.