Through silicon via and method of forming the same
US8841755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2013 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Jul 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on a surface of the via opening. The barrier layer is disposed on a surface of the insulation layer. The buffer layer is disposed on a surface of the barrier layer. The conductive electrode is disposed on a surface of the buffer layer and a remainder of the via opening is completely filled with the conductive electrode. A portion of the buffer layer further covers a surface of the conductive electrode at a side of the second surface and said portion is level with the second surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.