Data retention flip-flop
US8841952B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2013 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | May 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0372
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) includes a flip-flop that stores data when the IC is in built-in self-test (BIST) mode. The flip-flop includes a master latch connected to a slave latch, which in turn is connected to a data retention latch. A control circuit is connected to the flip-flop. During normal operation, the master latch receives a data input signal, which is transmitted through the slave latch to another flip-flop of the IC. When the control circuit initiates BIST (scan testing), data stored in the slave latch is transferred to the data retention latch. Upon completion of BIST, the data stored in the retention latch is used to restore the flip-flop to its original state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.