Stacked wafer level package having a reduced size
US8847377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2012 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Mar 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.