Microelectronic device having metal interconnection levels connected by programmable vias
US8847395B2 · kind B2 · utility
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12References
12Claims
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Key dates
| Filing date | Jul 5, 2011 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Jul 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0225
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic device, including: a substrate and a plurality of metal interconnection levels stacked on the substrate; a first metal line of a given metal interconnection level; a second metal line of another metal interconnection level located above the given metal interconnection level, the first and second lines are interconnected via at least one semiconductor connection element extending in a direction forming a nonzero angle with the first metal lines and the second metal line; and a gate electrode capable of controlling conduction of the semiconductor connection element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.