Inventor · Paris, FR

Sylvain Maitrejean

23Patents
2h-index
41Co-inventors
53Inventor score

Filing activity: Dec 19, 2008 → Jun 24, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US9502558B2 Local strain generation in an SOI substrate Electricity 4 Active
US10600786B2 Method for fabricating a device with a tensile-strained NMOS transistor and a uniaxial compression strained PMOS transistor Electricity 2 Active
US9853124B2 Method for fabricating a nanowire semiconductor transistor having an auto-aligned gate and spacers Electricity 2 Active
US9761607B2 Method for producing strained semi-conductor blocks on the insulating layer of a semi-conductor on insulator substrate Electricity 2 Active
US9704709B2 Method for causing tensile strain in a semiconductor film Electricity 2 Active
US9230991B2 Method to co-integrate oppositely strained semiconductor devices on a same substrate Electricity 1 Active
US9536951B2 FinFET transistor comprising portions of SiGe with a crystal orientation [111] Electricity 1 Active
US11195711B2 Healing method before transfer of a semiconducting layer Electricity 1 Active
US11424121B2 Method for forming a layer by cyclic epitaxy Electricity 0 Active
US11694991B2 Method for transferring chips Electricity 0 Active
US10978594B2 Transistor comprising a channel placed under shear strain and fabrication process Electricity 0 Active
US11081463B2 Bonding method with electron-stimulated desorption Electricity 0 Active
US8847395B2 Microelectronic device having metal interconnection levels connected by programmable vias Electricity 0 Active
US12198940B2 Method for modifying the strain state of a block of a semiconducting material Electricity 0 Active
US12322717B2 Semiconductor device and method for manufacturing a semiconductor device Electricity 0 Active
US11688811B2 Transistor comprising a channel placed under shear strain and fabrication process Electricity 0 Active
US8367547B2 Method for creating a metal crystalline region, in particular in an integrated circuit Electricity 0 Active
US10879083B2 Method for modifying the strain state of a block of a semiconducting material Electricity 0 Active
US10665497B2 Method of manufacturing a structure having one or several strained semiconducting zones that may for transistor channel regions Electricity 0 Active
US8114777B2 Horizontal nanotube/nanofiber growth method Electricity 0 Active
US11810789B2 Method of fabricating a semiconductor substrate having a stressed semiconductor region Electricity 0 Active
US9460971B2 Method to co-integrate oppositely strained semiconductor devices on a same substrate Electricity 0 Active
US9853130B2 Method of modifying the strain state of a semiconducting structure with stacked transistor channels Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.