Semiconductor structure with passive element network and manufacturing method thereof
US8853819B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2011 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Jun 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a semiconductor structure having an integrated passive network and a method for making the same. The semiconductor structure includes a substrate which can be an interposer. The substrate can include a plurality of conductive vias. In various embodiments, the substrate includes a dielectric layer disposed thereon, the dielectric layer having an opening forming a straight hole allowing electrical connection between the passive network and the conductive via. The passive network includes a series of patterned dielectric and conductive layers, forming passive electronic components. In an embodiment, the passive device includes a common resistor coupled to a pair of inductors, each of the inductors coupled to a capacitor. In another embodiment, the passive device includes a resistor and an inductor electrically connected to each other, a bottom surface of the inductor coplanar with a bottom surface of the resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.