Semiconductor structures including sub-resolution alignment marks
US8853868B2 · kind B2 · utility
3Cited by
18References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2013 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Oct 22, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24322
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating semiconductor structures comprising sub-resolution alignment marks is disclosed. The method comprises forming a dielectric material on a substrate and forming at least one sub-resolution alignment mark extending partially into the dielectric material. At least one opening is formed in the dielectric material. Semiconductor structures comprising the sub-resolution alignment marks are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.