Memory devices, architectures and methods for memory elements having dynamic change in property
US8854873B1 · kind B1 · utility
12Cited by
18References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2012 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Jul 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0088
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device can include at least one array comprising a plurality of elements programmable between at least two different states, each state having a different time to a change in property under applied sense conditions; a read circuit configured to apply the sense conditions to selected elements and detect changes in property of the selected elements to generate read data; a latch circuit configured to store read data from the read circuit; and a transfer path configured to provide a parallel data transfer path between the read circuit and the latch circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.