Static random access memory apparatus and bit-line voltage controller thereof
US8854897B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 1, 2012 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Apr 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory apparatus and a bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.