Method of packaging semiconductor die with cap element
US8859336B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2012 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Nov 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of assembling semiconductor devices includes placing an array of semiconductor dies on a die support. A cap array structure is provided that has a corresponding array of caps supported by a cap frame structure. The cap array structure and the array of semiconductor dies on the die support are aligned, with the caps extending over corresponding semiconductor dies, in a mold chase. The array of semiconductor dies and the array of caps are encapsulated with a molding compound in the mold chase. The encapsulated units of the semiconductor dies with the corresponding caps are removed from the mold chase and singulated. Singulating the encapsulated units may include removing the cap frame structure from the encapsulated units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.