Structure and method for making crack stop for 3D integrated circuits
US8859390B2 · kind B2 · utility
5Cited by
18References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2010 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Aug 17, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12044
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.