Software and method for via spacing in a semiconductor device
US8859416B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2012 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Dec 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/981
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A computer-readable software product is provided for executing a method of determining the location of a plurality of power rail vias in a semiconductor device. The semiconductor device includes an active region and a power rail. Locations of a first via and a second via are assigned along the power rail. The spacing between the location of the first via and the location of the second via is a minimum spacing allowable. The spacing between the location of the second via and the locations of structures in the active region which may electrically interfere with the second via is determined. The location of the second via is changed in response to the spacing between the location of the second via and the location of one of the structures in the active region being less than a predetermined distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.