Set/reset algorithm which detects and repairs weak cells in resistive-switching memory device
US8861258B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2013 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Jun 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistance-switching memory cell is programmed in a set or reset operation which tests the stability of the cell. A first programming phase using program voltages which increase in magnitude or duration until a program verify test is passed. A stability test phase is then performed to evaluate a stability of the memory cell. The stability test phase determines whether the memory cell is weak and likely to transition out of the set or reset state by applying one or more disturb pulses and performing one or more stability verify tests. The disturb pulses can have a reduced magnitude or duration compared to the program voltages. If the stability test phase indicates the memory cell is not stable, a second programming phase is performed. If the stability test phase indicates the memory cell is stable, the operation is concluded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.