Method and apparatus for program and erase of select gate transistors
US8861282B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2013 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | May 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their Vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells. Or, a decision can be made to program the select gate transistors based on a count of program-erase cycles, whether a specified time period has elapsed and/or a temperature history of the non-volatile storage device. When an erase command is made to erase memory cells, the select gate transistors are read to determine whether their Vth is above an acceptable range. If their Vth is above the acceptable range, the select gate transistors can be erased concurrently with the erasing of the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.