Adjustment of write timing based on error detection techniques
US8862966B2 · kind B2 · utility
4Cited by
3References
27Claims
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Key dates
| Filing date | Jul 30, 2010 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Sep 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.