Characterization based buffering and sizing for system performance optimization
US8863058B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2012 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Oct 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for timing optimization of an integrated circuit design using a timing optimization system comprising loading an original delay value and an original gate configuration net-list for an original gate from a results database. A near optimum gate configuration is identified using near optimum gate configuration information stored in a delay characterization database for the original gate. A near optimum delay value and a near optimum gate configuration net-list of a near optimum gate configuration are loaded. A timing optimized gate configuration is provided from running an incremental static timing analysis of the near optimum gate configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.