Hybrid gate last integration scheme for multi-layer high-k gate stacks
US8865581B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 19, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Dec 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28194
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a dual workfunction semiconductor device using a hybrid gate last integration scheme is described. According to one embodiment, the method includes heat-treating a first high-k film at a first heat-treating temperature to diffuse a first chemical element from a first cap layer into the first high-k film in a device region to form a first modified high-k film. The method further includes a gate-last processing scheme to form recessed features defined by sidewall spacers in the device regions and depositing a second high-k film in the recessed features. Some embodiments include forming an oxygen scavenging layer on the first high-k film, where the heat-treating the first high-k film scavenges oxygen from an interface layer to eliminate or reduce the thickness of an interface layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.