Power compensation in 3DIC testing

US8866488B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Mill-Jer Wang · Hsinchu, TW
• Ching-Nen Peng · Hsinchu, TW
• Hung-Chih Lin · Baoshan, TW
• Hao Chen

Key dates

• Filing date: Mar 22, 2011
• Grant date: Oct 21, 2014
• Expiry date: Jun 10, 2033

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/2886
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A device, such as a 3DIC stacked device includes a first device under test (DUT) connected to a first force pad by a first through substrate via (TSV) stack and connected to a first sense pad by a second TSV stack. The device further includes a second DUT stacked above the first DUT and connected to a second force pad and a second force pad by a second third TSV and connected to a second sense pad by a fourth TSV. Functional blocks on either the first or second blocks can be accessed for testing by way of the TSVs. In some applications the TSVs are vertically aligned to form TSV stacks.