Verification and debugging using heterogeneous simulation models
US8868396B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2009 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Mar 4, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for verifying and debugging a circuit design module of a high level programming system is disclosed herein. A circuit design created in a high level programming environment must undergo a number of transformations as it is compiled into a form that can be realized in hardware. At each transformative step, the behavior of the circuit must be verified with a simulation model and debugged if the transformation has changed the behavior of the circuit. The claimed invention presents a novel approach for verifying and debugging between different simulation models and achieves an advance in the art by utilizing the modularized structure of a high-level circuit design to systematically identify simulation mismatches among different simulation models and determine which portions of the circuit design are responsible for the discrepancy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.