Parameterized cell layout generation guided by a design rule checker
US8869084B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 24, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Nov 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating a layout for a cell of an integrated circuit (IC) guided by design rule checking (DRC) is disclosed. In the method, a model is defined, wherein the model comprises a plurality of parameters for generating a layout of the cell. Next an initial layout for the cell can be generated according to an initial set of values for the plurality of parameters. Then design rule checking (DRC) is performed for the initial layout based on a set of design rules. If any violations are found, the corresponding violation reports will be associated with the model. Therefore, a new set of values for the plurality of parameters can be generated by analyzing the violation reports collectively based on the model. With the new set of values for the plurality of parameters and above steps repeated, until no violation is found, a “DRC clean” layout can be generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.