Replacement source/drain finFET fabrication
US8871584B2 · kind B2 · utility
6Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2012 |
| Grant date | Oct 28, 2014 |
| Priority date | — |
| Expiry date | Jul 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched to expose a first region of the fin. A portion of the first region is then doped with a dopant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.