Patent · US Active

Data forwarding circuits and methods for memory devices with write latency

US8873264B1 · kind B1 · utility

0Cited by

15References

19Claims

0Family size

Assignee

Cypress Semiconductor Corporation · US

Inventors

Thinh Tran · Palo Alto, US
Joseph Tzou · Belmont, US

Key dates

Filing date	Mar 12, 2013
Grant date	Oct 28, 2014
Priority date	—
Expiry date	Mar 12, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG11C15/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory device can include a memory array section; a write first-in-first-out circuit (FIFO) configured to transfer write data to the memory array portion; at least one store circuit configured to store a copy of at least a portion of the write data stored in the write FIFO; and an address compare section configured to store write addresses corresponding to the write data of the forwarding circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.