Semiconductor memory apparatus and test circuit therefor
US8873272B2 · kind B2 · utility
407Cited by
1References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2011 |
| Grant date | Oct 28, 2014 |
| Priority date | — |
| Expiry date | Oct 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor memory apparatus, including: a memory cell array configured to include a plurality of memory cells; a switching unit configured to be coupled to data input and output pads and control a data transfer path of data applied to the data input and output pads in response to a test mode signal; a write driver configured to drive data transferred from the switching unit and write the data in the memory cell array at a normal mode; and a controller configured to transfer the data from the switching unit to the memory cell at a test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.